IET

'Low power design methodologies for nonometer SoC design' Patrick Groeneveld, University of Technology, The Netherlands

Access your personal account

Log in to see your favourites, lists and progress.

Access via institution

Not currently connected to any institutions

Connect via

Access Code

Redeem Access Code

Log in to redeem access code

This video isn’t available to you right now

Login to check your access and watch the full session.
To redeem an access code, first log in.

Login

Low power design methodologies for nanometer SoC design

Session
Wednesday, 17 November 2004
00:00
Duration: 40 mins
Publication date: 17 Nov 2004
Location: IETTV_Room, IETTV_Venue, London, United Kingdom
Part of event 1st IEE EDA Tools Forum

About the session

This presentation discusses low-power design methodologies for nm-scale silicon-on-chip (SoC) design.

Channels

Electronics

Electronics