Harmonic noise reduction in three-level inverter using space vector-based dithered sigma-delta modulator

Inverters using deterministic switching schemes produce switching noises concentrated on the harmonic frequencies. To suppress the harmonic spikes in three phase three-level voltage source inverters, a space vector-based dithered sigma-delta modulation scheme is proposed. In the proposed scheme, the instantaneous reference-voltage space vector is synthesized by a dithered sigma-delta analog-to-digital converter. The spurious harmonic spikes at the output of the sigma-delta modulator with regular input areeliminated by introducing a dithered sequence in the dithered sigma-delta modulator. The switching frequency of the dithered sigma-delta converter varies randomly, resulting in the spreading of the power spectrum of the inverter. The minimum pulse width of the output pulse train is the sampling time period, which prevents the inverter from missing switching operations. In the present work, the quantizer in the sigma-delta converter uses the principle of vector quantization instead of the conventional scalar quantizer. In this study, the space vectors are represented in the 60° coordinate system to reduce the computational complexity compared to the conventional Cartesian coordinate system. Experimental results of proposed scheme are compared with the space vector-based sigma-delta modulator, the space-vector pulse width modulation (SVPWM) scheme and the random PWM (pulse width modulation) scheme.