IET

Design for SoC Yield and Reliability Yervant Zorian, Vice-President and Chief Scientist, Virage Logic, USA

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Design for SoC Yield and Reliability

Session
Tuesday, 16 November 2004
00:00
Duration: 43 mins
Publication date: 16 Nov 2004
Location: IETTV_Room, IETTV_Venue, London, United Kingdom
Part of event 1st IEE EDA Tools Forum

About the session

This presentation discusses silicon-on-a-chip (SoC) design methods for achieving maximum yield and reliability.

Channels

Electronics

Electronics