Testing in the year 2020

Testing today's 500 million transistors SoCs with analogue, RF blocks, many processor cores and tens of memories is a huge task. What would test technology be like in ten years with hundreds of billions of transistors on a single chip? Can we get there with tweaks to today's technology? Adaptive power and frequency management techniques will need more cost-effective design structures (DFx) to improve testing and validation. Fault tolerance techniques at both the hardware and software levels will be mandatory to provide resilience/graceful degradation form soft errors, timing errors, defects, device degradation and signal integrity issues.