Plug and play memory test, repair and programmability from RTL planning

ICs developed at advanced technology nodes of 65nm and below have extremely complex test requirements. They integrate logic, 100's of embedded memories, and analog circuits, and require a mix of external test and built-in self test. This presentation discusses the complexities of SoC testing and describes a hierarchical test flow that can simplify the design-for-test challenge while increasing the quality and reliability of testing. It addresses design-for-test (DFT) and test implementation in the context of complex SoCs using multiple IP cores, and describes how to achieve large productivity gains by reusing tests developed for individual cores and mapping them to the full SoC. It also describes techniques for rapid test bring-up and debugging to save more time and accelerate time to market.