Panel Discussion II. Analog: the New Bottleneck!

Despite being only a fraction of the overall chip content, analog design is now dominating both the critical design path and the yield/failure mechanisms. Therefore, it is high time all stakeholders took a more critical view of analog design. Whether an EDA vendor, Fabless/IDM, contract designer or foundry, we all need to re-assess design tools and practices to ensure we can achieve right first time design in a reasonable timeframe, and thus can all reach profitability sooner. This panel discussion explores what can be done in EDA, design and foundry to improve design knowledge, practice and efficiency in order to ensure that "right first time" becomes the expectation it once was, and not the vain hope it has become.