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Condenser: Noun, an Apparatus for Compiling Science to the Cloud

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Presentation
  • Session
  • Monday, 10 November 2025
  • 16:10 - 16:10
  • Duration: 30 mins
  • Publication date: 11 Nov 2025
  • Location: Turing Lecture Theatre, IET London: Savoy Place, London, United Kingdom
  • Part of event REACH 2025

About the session

Albert Cohen, Research Scientist, Google DeepMind, France

Advances in ML acceleration hardware offer unprecedented opportunities to scale up scientific computing. What about large scale simulations on specialized tensor accelerators with state-of-the-art interconnect technology, also complementing traditional numerical methods with ML modeling? This is where condensers come in: no more vaporware of science in the cloud, but real-world automatic parallelization through domain-specific compilers. Unfortunately scientific applications are built for traditional HPC systems, often written in Fortran, C++ or more recently Julia, and remain largely incompatible with these technologies. Portable abstractions exist, such as Kokkos in C++, but remain much lower level than the compute graphs of popular ML frameworks. The abstraction and domain-specialization gap isolates scientific computing from rapid cloud-based innovation for AI workloads. With a compiler-centric focus, we will showcase recent achievements porting a Julia-based ocean model to both GPU- and Google TPU-based hardware, leveraging the MLIR infrastructure. We will highlight scientific and engineering challenges met along the way, as well as our original path to leverage cutting-edge ML infrastructure, from collective communications to low-level code generation and automatic differentiation.

Keywords:
  • IET conference
  • REACH 2025
  • Reach Emerging Architectures in Computing Horizons
  • Savoy Place London
  • Sustainable Computer System Design
  • emerging AI hardware
  • memory bandwidth problem

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Speaker

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    Albert Cohen

    Google DeepMind, France, Research Scientist

    Albert's research interests include program optimization for high-performance architectures and embedded systems, parallel data-flow programming, automatic parallelization and compiler support for parallel languages. He graduated from École Normale Supérieure de Lyon, and received his PhD from the University of Versailles in 1999 (awarded two national prizes). He is on leave from Inria, where he has been a (Senior) Research Scientist from 2000 to 2018. He has been a visiting scolar at the University of Illinois for six months in 2000 and 2001, a visiting professor at Philips Research and NXP Research for four months in 2006 and 2007, a visiting scientist at Facebook Artificial Intelligence Research for 6 months in 2017 and 2018, and held a teaching position as a part-time associate-professor at École Polytechnique from 2012 to 2015. He has coauthored more than 200 papers in refereed journals, international conferences and workshops, and he is or has been the advisor for 28 PhD theses.Specialties: Program optimization, parallel programming, optimizing compilation, automatic parallelization, machine learning applied to compilation, hardware acceleration for machine learning, synchronous programming, data-flow and synchronous programming, adaptive compilation, static analysis, embedded systems, high-performance computing.
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