Scaling Routes in Silicon Photonics

Silicon photonics has come a long way in its evolution from research to industrial uptake. Today between 5 and 10 industrial and semi-industrial platforms manufacture an estimated 5-10 million silicon photonics chips annually, mostly for high-speed datacenter transceivers. 

Are these volumes already large enough to create a sustainable ecosystem? 

What does it take to scale the production volumes by 10x in the next 10 years? Will there be a trend towards larger chips (scaling of integration level) or towards more chips (bigger markets, new markets), or both? Can new markets be served with the existing platforms, or do we need new process flows, or new combinations of process flows? How will heterogeneous integration come into play and how will it be brought on board of the supply chains? 

Speakers (Please continue scrolling down for further information on each talk)

The workshop moderators may shuffle the program for better linkage between the talks of various speakers. 

Heterogeneous integration as enabling technology for Silicon Photonics scaling

Thomas Liljeberg, Intel

With annual unit shipments in the millions, an expanding foundry ecosystem, and growing market share in currently addressed segments, Silicon Photonics technology arguably is already at scale and maturity.  Future requirements e.g. in AI/ML infrastructure provide the opportunity for the next order-of-magnitude growth in production volumes, but fully realizing this potential requires advances along multiple vectors, including manufacturability, cost, performance, and density.  Focusing primarily on the AI opportunity, we review the challenges and outline how heterogeneous integration approaches may address these challenges and enable the next big shift in where and how photonics is deployed.

Scaling routes: Towards SiPho 2.0?

Frédéric Boeuf, STMicro

After 3 decades of research, Silicon Photonics has been existing in major CMOS fabs for more than 10 years. Seen as a high-volume and low cost solution for optical communication products, SiPho market share has been progressing slowly and shipped volumes are remaining low compared to traditional CMOS technologies.  Nevertheless, SiPho potential remains very high by addressing the scaling challenge of several applications, making it the technology of choice for future products in data communication, optical I/O, sensing, computing etc..

In order to capture these markets Silicon Photonics platform will have to evolve towards SiPho2.0, with more process complexity and integration of heterogeneous materials. In the presentation we'll show the R&D platform developed at STMicroelectronics and some examples of the research work done to extend the application field of our technology.

Scaling Routes in SiPh for Test, Assembly and Packaging of PICs

Kamil Gradkowski, Tyndall National Institute

Packaging and testing of PIC-based photonic devices is a very costly part of the entire assembly process. This is due to a combination of the high precision required for the alignment of fibres to the chip and the serial nature of the packaging process. In this talk, I will present developments in the area of pluggable photonics, where the package and the fibre are separated by an air gap and the optical connection is mediated via micro-lenses that expand and collimate the beam. I will show how such an approach will lead to wafer- and panel-scale device packaging and testing and, in utilizing low-cost glass platforms, economies of scale and machines available in the microelectronic industry, the cost of assembly of photonic chips can be reduced, lowering the barrier to entry for new ideas, companies and markets.

Data Center Infrastructure Technology Adoption Challenges: SiPh perspective 

Drew Alduino, Meta

 IO demands continue to grow, driven by AI/ML cluster architectures to support new and emerging workloads and increasingly complex and diverse models (Metaverse, GenAI, etc); co-package integration with SiPh seems a likely technology to address these BW demands, but the technology must offer a system TCO benefit when compared to incumbent electrical solutions.  Barriers to adoption will include unknown technical risks, supply chain complexity and manufacturability.  A multi-vendor ecosystem with standardized electrical, optical and physical interfaces is desirable, as differentiated hardware solutions/platforms are very difficult to adopt at DC scale without a proven track record of success.  We propose several paths to adoption based upon industry maturity.