Module Packaging Trends

Technology shifts and advances in consumer electronics and, specifically, in wireless applications create a long list of challenges for chip and system design. The number of transistors required to enable new features and functionality - coupled with shrinking die sizes and higher clock speeds needed for improved levels of performance - are driving IC designers to use smaller process nodes. Additionally, IO counts are skyrocketing as more functionality is built into the die. As more designs transition to mixed-mode modules consisting of analog and digital capabilities (e.g. an RF chip with a base band module, the addition of passive components such as an antennae and different memory technologies), more efficient and cost-effective means are required to combine these applications where including them may compromise the choice of process technology. In addition, as these technologies combine to form a system versus a full chip, changes in testing approaches must be accounted for. This presentation addresses digital chips and mixed-signal combinations in a single package, with emphasis on system-in-package (SiP) applications. It is forecast that multi-die packaging applications will grow substantially over the next several years, so this presentation sheds light on this topic by illuminating case studies, providing best practices and general guidelines on how to evaluate the tradeoffs.