Massively Parallel Architectures

The 'memory wall' problem is a major contributing factor to limiting processor performance which is a result of memory access times not matching the dramatic increases in processor speeds. Traditionally, the memory wall problem has been overcome by introducing extra levels in the memory hierarchy. Unfortunately, such an approach also increases the design complexity and power consumption of the overall computer system. Furthermore, there is an increase in the penalty associated with a miss in the memory-subsystem resulting in a limitation of the exploitation of instruction level parallelism (ILP).