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Diversified technologies for system-on-chip

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Conference
  • Session
  • Wednesday, 18 February 2004
  • 00:18 - 00:18
  • Duration: 30 mins
  • Publication date: 18 Feb 2004
  • Location: IETTV_Room, IETTV_Venue, Paris, France
  • Part of event DATE (Design, Automation and Test in Europe) 2004

About the session

Thanks to the continued progress in CMOS technology and manufacturing science, it is now possible to provide multiple process options that allow enhancement of particular aspects of the baseline CMOS, permitting designers to address specific product and application requirements. These requirements could be ultra low-noise RF performance, extremely high-speed digital performance, refined analogue precision, energy management (high voltage and current capabilities), very low bit-error rate memories and low power consumption. After a brief survey of the modular technology approaches allowing these extra functionalities to be supported, the speaker concentrates on different options in the technology and how they can be exploited to provide very low power consumption in complex SoCs. Finally, the speaker discusses the interactions that need to occur between designers, technologists and the wafer fab in order to provide easy prototyping access to the technology with first-time silicon success and rapid ramp-up to high yield.

Channels

Electronics

Electronics

Speaker

  • PM

    Philippe Magarshack

    STMicroelectronics, Central R&D Group, Group Vice President

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