Accelerating Time to Design Closure with Olymups - SoC

For ICs manufactured at nodes below 45nm, ensuring high performance and high manufacturing yield requires new approaches to physical design optimization and verification. Achieving design closure for power, signal integrity (SI) and manufacturing variability can be a lengthy process requiring many ECO loops if these considerations are only addressed after routing and timing closure is completed. In addition, foundries are instituting complex new routing rules for 32/28nm processes to ensure manufacturability that require native tool support. This presentation explains how to manage power, SI and design-for-manufacturing (DFM) issues throughout the implementation flow to improve productivity, reduce risk, and achieve optimal quality of results. It explains how architectural support for multi-corner-multi-mode (MCMM), advanced stag-based OCV analysis and optimization, advanced multi-Vdd methodologies, such as disjoint power domains and UPF hierarchical low power automation, and MCMM clock tree synthesis (CTS) can improve the performance of products and decrease time to market.