Exploiting State-of-the-Art Verification Techniques in VHDL Test Benches

For many FPGA and ASIC designers, VHDL continues to be the language-of-choice for digital design and verification. As a language, VHDL is mature, robust, well-understood, and well-supported by tool and service providers. However, the focus for the state-of-the-art in functional verification has now moved to other languages such as SystemVerilog and to methodologies such as OVM and UVM, the Open- and the Universal Verification Methodology, respectively. In this session we take the lessons learned from SystemVerilog and apply them to developing a best practice for VHDL test benches. We show how to structure a VHDL test bench into re-usable verification components such as drivers, monitors and test sequencers, introducing some advanced VHDL coding techniques for transaction-level modelling along the way. We also show how best to implement functional coverage collection and checking in VHDL, and how to take advantage of test planning to improve the quality of the verification process.