Paper from EDA Tech Forum organised by Mentor Graphics, Oxfordshire, UK, 22 June 2010, Track 1: Proven Approaches to Higher Productivity in the IC Design and Verification Flow
22 June 2010 Corporate presentations
Entering the second decade of the millennium, â€œlow powerâ€ is one of the few over-arching drivers electronic designers must continually address. Why is the market demanding more energy efficient products? Will advances in process technology magically rescue designers? Typically, the techniques used to improve the power characteristics of a design involve additional complexity on top of an already complex design and verification process. This presentation will explore the forces from technology and market perspectives that are driving designers towards better energy efficient designs. It will also discuss where the â€œgainâ€ from going through the additional â€œpainâ€ and what methods will achieve greater productivity.
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