Paper from EDA Tech Forum organised by Mentor Graphics, Oxfordshire, UK, 22 June 2010, Track 1: Proven Approaches to Higher Productivity in the IC Design and Verification Flow
22 June 2010 Corporate presentations
Many challenges confronting design teams at the functional verification stage are inhibiting the advancement to a 10x increase in verification productivity. It's obvious that we can't just brute force the problem by throwing more compute resources at it. Challenges addressed in the session include:
- Reaching 70-80% coverage is straight-forward using automated constrained random test methods. How can I reduce the time to achieve high levels of coverage and then quickly close the remaining coverage holes?
- Systems include software as well as hardware. Simulation is impractical for validating anything longer than a 10's or 100's of lines of software code. How can I speed up the process of verifying my systems?
- Systems include analog blocks within a majority digital SoC. How can I verify mixed signal functionality without dragging the verification efficiency to the level of a SPICE simulation?
- Debug brings humans in the verification loop creating a huge drag on productivity. How can I speed up the debug process?
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