Calibre Innovations to Reduce Your Signoff Cycle Time (Calibre: Calibre nmDRC Auto-waivers, Calibre Xact)
Barry Byford
Paper from EDA Tech Forum organised by Mentor Graphics, Oxfordshire, UK, 22 June 2010, Track 2: Beat Your Competition to Market with a Supercharged Design-to-Silicon Flow
22 June 2010 Corporate presentations
>> Play webcastThe challenges of manufacturing at sizes below 45nm are driving much more complex design rule checks and model-based design-for-manufacturing (DFM) analysis before signoff. Other competitive demands, such as achieving signoff on IP from many suppliers, more stringent Design for Reliability (DFR) checks, and tighter error tolerances on extraction and simulation, are all adding to the difficulty and time required to complete signoff. This session will introduce attendees to a range of new innovations that simplify and accelerate the signoff process, including:
• Equation-based DRC to speed DFM and other complex design rules
• Programmable Electrical Rule Checking (ERC) to improve reliability
• Auto-waivers to eliminate DRC violations that have already been waived by the foundry
• High-performance 3D extraction with full-chip capacity and field solver accuracy
This session provides designers with new tricks to beat the competition by speeding up their signoff process.
If you have any questions regarding this presentation please contact barry_byford@mentor.com